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MCP3905/06
Energy-Metering ICs with Active (Real) Power Pulse Output
Features
* Supplies active (real) power measurement for single-phase, residential energy-metering * Supports the IEC 62053 International Energy Metering Specification and legacy IEC 1036/61036/687 Specifications * Two multi-bit, Digital-to-Analog Converters (DACs), second-order, 16-bit, Delta-Sigma Analog-to-Digital Converters (ADCs) * 0.1% typical measurement error over 500:1 dynamic range (MCP3905) * 0.1% typical measurement error over 1000:1 dynamic range (MCP3906) * Programmable Gain Amplifier (PGA) for smallsignal inputs supports low-value shunt current sensor - 16:1 PGA - MCP3905 - 32:1 PGA - MCP3906 * Ultra-low drift on-chip reference: 15 ppm/C (typ.) * Direct drive for electromagnetic mechanical counter and two-phase stepper motors * Low IDD of 4 mA (typ.) * Tamper output pin for negative power indication * Industrial Temperature Range: -40C to +85C * Supplies instantaneous active (real) power on HFOUT for meter calibration
Description
The MCP3905/06 devices are energy-metering ICs designed to support the IEC 62053 International Metering Standard Specification. They supply a frequency output proportional to the average active (real) power, as well as a higher-frequency output proportional to the instantaneous power for meter calibration. They include two 16-bit, delta-sigma ADCs for a wide range of IB and IMAX currents and/or small shunt (< 200 Ohms) meter designs. It includes an ultra-low drift voltage reference with < 15 ppm/C through a specially designed band gap temperature curve for the minimum gradient across the industrial temperature range. A fixed-function DSP block is onchip for active (real) power calculation. Strong output drive for mechanical counters are on-chip to reduce field failures and mechanical counter sticking. A noload threshold block prevents any current creep measurements. A Power-On Reset (POR) block restricts meter performance during low-voltage situations. These accurate energy-metering ICs with high field reliability are available in the industry-standard pinout.
Package Type
24-Pin SSOP
DVDD HPF AVDD NC CH0+ CH0CH1CH1+ MCLR REFIN/OUT AGND F2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FOUT0 FOUT1 HFOUT DGND NEG NC OSC2 OSC1 G0 G1 F0 F1
US Patents Pending
Functional Block Diagram
G0 G1 HPF OSC1 OSC2 HFOUT CH0+ CH0+ PGA - 16-bit Multi-level ADC HPF1 F2 F1 F0 FOUT0 FOUT1 NEG
REFIN/ OUT 2.4V Reference
X
16-bit Multi-level ADC HPF1
LPF1
E-to-F conversion
CH1+ CH1-
+ -
POR MCLR
(c) 2005 Microchip Technology Inc.
DS21948C-page 1
MCP3905/06
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
VDD ...................................................................................7.0V Digital inputs and outputs w.r.t. AGND ........ -0.6V to VDD +0.6V Analog input w.r.t. AGND ..................................... ....-6V to +6V VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V Storage temperature .....................................-65C to +150C Ambient temp. with power applied ................-65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD on the analog inputs (HBM,MM) .................5.0 kV, 500V ESD on all other pins (HBM,MM) ........................5.0 kV, 500V
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V - 5.5V, Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40C to +85C. Parameter Sym Min -- -- Typ. 0.1 0.1 Max -- Units Comment Overall Measurement Accuracy Energy Measurement Error E
No-Load Threshold/ NLT -- 0.0015 Minimum Load Phase Delay Between -- -- Channels AC Power Supply AC PSRR -- 0.01 Rejection Ratio (Output Frequency Variation) DC Power Supply DC PSRR -- 0.01 -- % FOUT HPF = 1, Gain = 1 (Note 3) Rejection Ratio (Output Frequency Variation) System Gain Error -- 3 10 % FOUT Note 2, Note 5 ADC/PGA Specifications -- 2 5 mV Referred to Input Offset Error VOS Gain Error Match -- 0.5 -- % FOUT Note 8 Internal Voltage Reference Voltage -- 2.4 -- V Tolerance -- 2 -- % Tempco -- 15 -- ppm/C Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is measured with signal (660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz. See Section 2.0 "Typical Performance Curves" for higher frequencies and increased dynamic range. 2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between measured output frequency and expected transfer function. 3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V 500 mV. 4: Error applies down to 60 lead (PF = 0.5 capacitive) and 60 lag (PF = 0.5 inductive). 5: Refer to Section 4.0 "Device Overview" for complete description. 6: Specified by characterization, not production tested. 7: 1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz. 8: Gain error match is measured from CH0 G = 1 to any other gain setting.
% FOUT Channel 0 swings 1:500 range, MCP3905 only (Note 1, Note 4) -- % FOUT Channel 0 swings 1:1000 range, MCP3906 only (Note 1, Note 4) Disabled when F2, F1, F0 = 0, 1, 1 -- % FOUT Max (Note 5, Note 6) 1/MCLK s HPF = 0 and 1, < 1 MCLK (Note 4, Note 6, Note 7) -- % FOUT F2, F1, F0 = 0, 1, 1 (Note 3)
DS21948C-page 2
(c) 2005 Microchip Technology Inc.
MCP3905/06
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V - 5.5V, Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40C to +85C. Parameter Sym Min Typ. Max Units Comment Reference Input Input Range 2.2 -- 2.6 V Input Impedance 3.2 -- -- k Input Capacitance -- -- 10 pF Analog Inputs Maximum Signal Level -- -- 1 V CH0+,CH0-,CH1+,CH1- to AGND Differential Input Voltage -- -- 470/G mV G = PGA Gain on Channel 0 Range Channel 0 Differential Input Voltage -- -- 660 mV Range Channel 1 Input Impedance 390 -- -- k Proportional to 1/MCLK frequency Bandwidth -- 14 -- kHz Proportional to MCLK frequency, (Notch Frequency) MCLK/256 Oscillator Input Frequency Range MCLK 1 -- 4 MHz Power Specifications Operating Voltage 4.5 -- 5.5 V AVDD, DVDD IDD,A IDD,A -- 2.7 3.0 mA AVDD pin only IDD,D IDD,D -- 1.2 2.0 mA DVDD pin only Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is measured with signal (660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz. See Section 2.0 "Typical Performance Curves" for higher frequencies and increased dynamic range. 2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between measured output frequency and expected transfer function. 3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V 500 mV. 4: Error applies down to 60 lead (PF = 0.5 capacitive) and 60 lag (PF = 0.5 inductive). 5: Refer to Section 4.0 "Device Overview" for complete description. 6: Specified by characterization, not production tested. 7: 1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz. 8: Gain error match is measured from CH0 G = 1 to any other gain setting.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 4.5V - 5.5V, AGND, DGND = 0V. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Note: TA TA TA -40 -40 -65 -- -- -- +85 +125 +150 C C C Note Sym Min Typ Max Units Conditions
The MCP3905/06 operate over this extended temperature range, but with reduced performance. In any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C.
(c) 2005 Microchip Technology Inc.
DS21948C-page 3
MCP3905/06
TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V - 5.5V, AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40C to +85C. Parameter Frequency Output FOUT0 and FOUT1 Pulse Width (Logic-Low) HFOUT Pulse Width FOUT0 and FOUT1 Pulse Period HFOUT Pulse Period FOUT0 to FOUT1 Falling-Edge Time FOUT0 to FOUT1 Min Separation FOUT0 and FOUT1 Output High Voltage FOUT0 and FOUT1 Output Low Voltage HFOUT Output High Voltage HFOUT Output Low Voltage High-Level Input Voltage (All Digital Input Pins) Low-Level Input Voltage (All Digital Input Pins) Input Leakage Current Pin Capacitance Note 1: 2: 3: tFW tHW tFP tHP tFS2 tFS VOH VOL VOH VOL VIH VIL
--
Sym
Min
Typ 275
90
Max
-- --
Units ms ms s s
Comment 984376 MCLK periods (Note 1) 322160 MCLK periods (Note 2)
--
Refer to Equation 4-1 Refer to Equation 4-2
-- --
0.5 tFP 4/MCLK
-- -- -- -- -- -- -- --
-- -- --
4.5
--
V V V V V V A pF
IOH = 10 mA, DVDD = 5.0V IOL = 10 mA, DVDD = 5.0V IOH = 5 mA, DVDD = 5.0V IOL = 5 mA, DVDD = 5.0V DVDD = 5.0V DVDD = 5.0V VIN = 0, VIN = DVDD Note 3
0.5
--
4.0
--
0.5
--
2.4
-- -- --
0.85 3 10
If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP. If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP. Specified by characterization, not production tested.
tFP tFW FOUT0 tFS tFS2 FOUT1
tHW HFOUT tHP
NEG
FIGURE 1-1:
Output Timings for Pulse Outputs and Negative Power Pin.
DS21948C-page 4
(c) 2005 Microchip Technology Inc.
MCP3905/06
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode), MCLK = 3.58 MHz.
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0000 0.6 Measurement Error
+85C
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.0000
-40C +25C +85C
Measurement Error
+25C
-40C
0.0001
0.0010
0.0100
0.1000
0.0001
0.0010
0.0100
0.1000
CH1 Vp-p Amplitude (V)
CH1 Vp-p Amplitude (V)
FIGURE 2-1: Gain = 8, PF = 1.
0.5 Measurement Error
Measurement Error,
FIGURE 2-4: Measurement Error, Gain = 8, PF = 0.5.
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.0000
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.0000 0.0001 0.0010 0.0100 0.1000
- 40C +25C
Measurement Error
0.4
+85C
+85C
+25C
-40C
0.0001
0.0010
0.0100
0.1000
CH1 Vp-p Amplitude (V)
CH1 Vp-p Amplitude (V)
FIGURE 2-2: Measurement Error, Gain = 16, PF = 1.
0.8 Measurement Error
FIGURE 2-5: Measurement Error, Gain = 16, PF = 0.5.
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0.0000
0.4 0.2 0
- 40C +25C
Measurement Error
0.6
+85C
+85C +25C
-0.2 -0.4 -0.6 -0.8 0.0000 0.0001 0.0010 0.0100 0.1000
-40C
0.0001
0.0010
0.0100
0.1000
CH1 Vp-p Amplitude (V)
CH1 Vp-p Amplitude (V)
FIGURE 2-3: Measurement Error, Gain = 32, PF = 1.
FIGURE 2-6: Measurement Error, Gain = 32, PF = 0.5.
(c) 2005 Microchip Technology Inc.
DS21948C-page 5
MCP3905/06
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode), MCLK = 3.58 MHz.
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0001 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0001
Measurement Error
+85C
Measurement Error
+85C
+25C
+25C
- 40C
-40C
0.0010
0.0100
0.1000
1.0000
0.0010
0.0100
0.1000
1.0000
CH0 Vp-p Amplitude (V)
CH1 Vp-p Amplitude (V)
FIGURE 2-7: Gain = 1, PF = 1.
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0001
Measurement Error,
FIGURE 2-9: Measurement Error, Gain = 1, PF = + 0.5.
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.0001
Measurement Error
Measurement Error
+85C
+85C
+25C
+25C
- 40C
-40C
0.0010
0.0100
0.1000
1.0000
0.0010
0.0100
0.1000
1.0000
CH0 Vp-p Amplitude (V)
CH1 Vp-p Amplitude (V)
FIGURE 2-8: Gain = 2, PF = 1.
Measurement Error,
FIGURE 2-10: Measurement Error, Gain = 2, PF = + 0.5.
DS21948C-page 6
(c) 2005 Microchip Technology Inc.
MCP3905/06
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode), MCLK = 3.58 MHz.
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 45
4000 3500 3000 2500 2000 1500 1000 500 0
% Error
PF = 1.0
Occurance
PF = 0.5
16384 Samples Mean = - 1.28 mV Std. dev = - 18.1 V
50
55
60
65
70
75
Frequency (Hz)
FIGURE 2-11: Input Frequency.
3000
Measurement Error vs.
FIGURE 2-14: Channel 0 Offset Error (DC Mode, HPF Off), G = 16.
0.3 Measurement Error
2500 Occurance 2000 1500 1000 500 0
16384 Samples Mean = -1.57 mV Std. Dev = 52.5 V
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
VDD=5.5V VDD=5.25V VDD=4.5V VDD=4.75V VDD=5.0V
-1.75
-1.70
-1.65
-1.61
-1.56
-1.52
-1.47
-1.43
-1.38
-0.5 0.0001
Channel 0 Offset (mV)
FIGURE 2-12: Channel 0 Offset Error (DC Mode, HPF off), G = 1.
1200
FIGURE 2-15: (G = 16).
0.3 0.25 Measurement Error 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 0.0001
VDD=5.0V
1000 Occurance 800 600 400 200 0
16384 Samples Mean = -1.64 mV Std. Dev = 17.4 V
-1.71
-1.69
-1.68
-1.67
-1.66
-1.65
-1.64
-1.63
-1.62
-1.60
-1.59
Channel 0 Offset (mV)
FIGURE 2-13: Channel 0 Offset Error (DC Mode, HPF off), G = 8.
FIGURE 2-16: Measurement Error vs. VDD, G = 16, External VREF .
(c) 2005 Microchip Technology Inc.
-1.38E-03 -1.37E-03 -1.36E-03 -1.35E-03 -1.34E-03 -1.33E-03 -1.32E-03 -1.31E-03 -1.30E-03 -1.29E-03 -1.28E-03 -1.27E-03 -1.26E-03 -1.25E-03 -1.24E-03 -1.23E-03 -1.22E-03
Bin (mV)
0.0010
0.0100
0.1000
1.0000
CH0 Vp-p Amplitude (V)
Measurement Error vs. VDD
VDD=4.75V
VDD=4.5V
VDD=5.25V VDD=5.5V
0.0010
0.0100
0.1000
1.0000
CH0 Vp-p Amplitude (V)
DS21948C-page 7
MCP3905/06
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode), MCLK = 3.58 MHz.
0.3 Measurement Error Measurement Error 0.2 0.1
+85C
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.0000
- 40C +85C +25C
0 -0.1 -0.2 -0.3 0.0001
- 40C
+25C
0.0010
0.0100
0.1000
1.0000
0.0001
0.0010
0.0100
0.1000
CH0 Vp-p Amplitude (V)
CH1 Vp-p Amplitude (V)
FIGURE 2-17: Measurement Error w/ External VREF, (G = 1).
0.3 Measurement Error 0.2 0.1 0
-40C +25C +85C
FIGURE 2-19: Measurement Error w/ External VREF (G = 16).
-0.1 -0.2 -0.3 0.0000
0.0001
0.0010
0.0100
0.1000
CH1 Vp-p Amplitude (V)
FIGURE 2-18: Measurement Error w/ External VREF, (G = 8).
DS21948C-page 8
(c) 2005 Microchip Technology Inc.
MCP3905/06
3.0 PIN DESCRIPTIONS
PIN FUNCTION TABLE
Symbol DVDD HPF AVDD NC CH0+ CH0CH1CH1+ MCLR REFIN/OUT AGND F2 F1 F0 G1 G0 OSC1 OSC2 NC NEG DGND HFOUT FOUT1 FOUT0 Digital Power Supply Pin High-Pass Filters Control Logic Pin Analog Power Supply Pin No Connect Non-Inverting Analog Input Pin for Channel 0 (Current Channel) Inverting Analog Input Pin for Channel 0 (Current Channel) Inverting Analog Input Pin for Channel 1 (Voltage Channel) Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel) Master Clear Logic Input Pin Voltage Reference Input/Output Pin Analog Ground Pin, Return Path for internal analog circuitry Frequency Control for HFOUT Logic Input Pin Frequency Control for FOUT0/1 Logic Input Pin Frequency Control for FOUT0/1 Logic Input Pin Gain Control Logic Input Pin Gain Control Logic Input Pin Oscillator Crystal Connection Pin or Clock Input Pin Oscillator Crystal Connection Pin or Clock Output Pin No Connect Negative Power Logic Output Pin Digital Ground Pin, Return Path for Internal Digital Circuitry High-Frequency Logic Output Pin (Intended for Calibration) Differential Mechanical Counter Logic Output Pin Differential Mechanical Counter Logic Output Pin Function The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
3.1
Digital VDD (DVDD)
3.3
Analog VDD (AVDD)
DVDD is the power supply pin for the digital circuitry within the MCP3905/06. DVDD requires appropriate bypass capacitors and should be maintained to 5V 10% for specified operation. Please refer to Section 5.0 "Applications Information".
AVDD is the power supply pin for the analog circuitry within the MCP3905/06. AVDD requires appropriate bypass capacitors and should be maintained to 5V 10% for specified operation. Please refer to Section 5.0 "Applications Information".
3.2
High-Pass Filter Input Logic Pin (HPF)
3.4
Current Channel (CH0-, CH0+)
HPF controls the state of the high-pass filter in both input channels. A logic `1' enables both filters, removing any DC offset coming from the system or the device. A logic `0' disables both filters, allowing DC voltages to be measured.
CH0- and CH0+ are the fully differential analog voltage input channels for the current measurement, containing a PGA for small-signal input, such as shunt currentsensing. The linear and specified region of this channel is dependant on the PGA gain. This corresponds to a maximum differential voltage of 470 mV/GAIN and maximum absolute voltage, with respect to AGND, of 1V. Up to 6V can be applied to these pins without the risk of permanent damage. Refer to Section 1.0 "Electrical Characteristics".
(c) 2005 Microchip Technology Inc.
DS21948C-page 9
MCP3905/06
3.5 Voltage Channel (CH1-,CH1+) 3.11 Oscillator (OSC1, OSC2)
CH1- and CH1+ are the fully differential analog voltage input channels for the voltage measurement. The linear and specified region of these channels have a maximum differential voltage of 660mV and a maximum absolute voltage of 1V, with respect to AGND. Up to 6V can be applied to these pins without the risk of permanent damage. Refer to Section 1.0 "Electrical Characteristics". OSC1 and OSC2 provide the master clock for the device. A resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 3.579545 MHz. However, the clock frequency can be with the range of 1 MHz to 4 MHz without disturbing measurement error. Appropriate load capacitance should be connected to these pins for proper operation. A full-swing, single-ended clock source may be connected to OSC1 with proper resistors in series to ensure no ringing of the clock source due to fast transient edges.
3.6
Master Clear (MCLR)
MCLR controls the reset for both delta-sigma ADCs, all digital registers, the SINC filters for each channel and all accumulators post multiplier. A logic `0' resets all registers and holds both ADCs in a Reset condition. The charge stored in both ADCs is flushed and their output is maintained to 0x0000h. The only block consuming power on the digital power supply during Reset is the oscillator circuit.
3.12
Negative Power Output Logic Pin (NEG)
3.7
Reference (REFIN/OUT)
REFIN/OUT is the output for the internal 2.4V reference. This reference has a typical temperature coefficient of 15 ppm/C and a tolerance of 2%. In addition, an external reference can also be used by applying voltage to this pin within the specified range. REFIN/OUT requires appropriate bypass capacitors to AGND, even when using the internal reference only. Refer to Section 5.0 "Applications Information".
NEG detects the phase difference between the two channels and will go to a logic `1' state when the phase difference is greater than 90 (i.e., when the measured active (real) power is negative). The output state is synchronous with the rising-edge of HFOUT and maintains the logic `1' until the active (real) power becomes positive again and HFOUT shows a pulse.
3.13
Ground Connection (DGND)
3.8
Analog Ground (AGND)
AGND is the ground connection to the internal analog circuitry (ADCs, PGA, band gap reference, POR). To ensure accuracy and noise cancellation, this pin must be connected to the same ground as DGND, preferably with a star connection. If an analog ground plane is available, it is recommended that this device be tied to this plane of the Printed Circuit Board (PCB). This plane should also reference all other analog circuitry in the system.
DGND is the ground connection to the internal digital circuitry (SINC filters, multiplier, HPF, LPF, Digital-toFrequency (DTF) converter and oscillator). To ensure accuracy and noise cancellation, DGND must be connected to the same ground as AGND, preferably with a star connection. If a digital ground plane is available, it is recommended that this device be tied to this plane of the PCB. This plane should also reference all other digital circuitry in the system.
3.14
High-Frequency Output (HFOUT)
3.9
Frequency Control Logic Pins (F2, F1, F0)
F2, F1 and F0 select the high-frequency output and low-frequency output pin ranges by changing the value of the constants FC and HFC used in the device transfer function. FC and HFC are the frequency constants that define the period of the output pulses for the device.
HFOUT is the high-frequency output of the device and supplies the instantaneous real-power information. The output is a periodic pulse output, with its period proportional to the measured active (real) power, and to the HFC constant defined by F0, F1 and F2 pin logic states. This output is the preferred output for calibration due to faster output frequencies, giving smaller calibration times. Since this output gives instantaneous active (real) power, the 2 ripple on the output should be noted. However, the average period will show minimal drift.
3.15
Frequency Output (FOUT0, FOUT1)
3.10
Gain Control Logic Pins (G1, G0)
G1 and G0 select the PGA gain on Channel 0 from three different values: 1, 8 and 16.
FOUT0 and FOUT1 are the frequency outputs of the device that supply the average real-power information. The outputs are periodic pulse outputs, with its period proportional to the measured active (real) power, and to the Fc constant, defined by the F0 and F1 pin logic states. These pins include high-output drive capability for direct use of electromechanical counters and 2phase stepper motors. Since this output supplies average active (real) power, any 2 ripple on the output pulse period is minimal.
DS21948C-page 10
(c) 2005 Microchip Technology Inc.
MCP3905/06
4.0 DEVICE OVERVIEW
The MCP3905/06 is an energy-metering IC that supplies a frequency output proportional to active (real) power, and higher frequency output proportional to the instantaneous power for meter calibration. Both channels use 16-bit, second-order, delta-sigma ADCs that oversample the input at a frequency equal to MCLK/4, allowing for wide dynamic range input signals. A Programmable Gain Amplifier (PGA) increases the usable range on the current input channel (Channel 0). The calculation of the active (real) power, as well as the filtering associated with this calculation, is performed in the digital domain, ensuring better stability and drift performance. Figure 4-1 represents the simplified block diagram of the MCP3905/06, detailing its main signal-processing blocks. Two digital high-pass filters cancel the system offset on both channels such that the real-power calculation does not include any circuit or system offset. After being high-pass filtered, the voltage and current signals are multiplied to give the instantaneous power signal. This signal does not contain the DC offset components, such that the averaging technique can be efficiently used to give the desired active (real) power output. The instantaneous power signal contains the realpower information; it is the DC component of the instantaneous power. The averaging technique can be used with both sinusoidal and non-sinusoidal waveforms, as well as for all power factors. The instantaneous power is thus low-pass filtered in order to produce the instantaneous real-power signal. A DTF converter accumulates the instantaneous active (real) power information to produce output pulses with a frequency proportional to the average active (real) power. The low-frequency pulses presented at the FOUT0 and FOUT1 outputs are designed to drive electromechanical counters and two-phase stepper motors displaying the real-power energy consumed. Each pulse corresponds to a fixed quantity of real energy, selected by the F2, F1 and F0 logic settings. The HFOUT output has a higher frequency setting and lower integration period such that it can represent the instantaneous active (real) power signal. Due to the shorter accumulation time, it enables the user to proceed to faster calibration under steady load conditions (refer to Section 4.7 "FOUT0/1 and HFOUT Output Frequencies").
CH0+ CH0-
+ - PGA
MCP3905/06
ADC DIGITAL
HPF
ANALOG
CH1+ CH1-
X
LPF
..0101...
FOUT0 FOUT1 HFOUT
DTF
+ -
ADC
HPF
Frequency Content
0
0 0 0 0
Input Signal with System Offset and Line Frequency
ADC Output Code Contains System and ADC Offset
DC Offset Removed by HPF
Instantaneous Power
Instantaneous Active (Real) Power
FIGURE 4-1:
Simplified MCP3905/06 Block Diagram with Frequency Contents.
(c) 2005 Microchip Technology Inc.
DS21948C-page 11
MCP3905/06
4.1 Analog Inputs
The MCP3905/06 analog inputs can be connected directly to the current and voltage transducers (such as shunts or current transformers). Each input pin is protected by specialized Electrostatic Discharge (ESD) structures that are certified to pass 5 kV HBM and 500V MM contact charge. These structures also allow up to 6V continuous voltage to be present at their inputs without the risk of permanent damage. Both channels have fully differential voltage inputs for better noise performance. The absolute voltage at each pin relative to AGND should be maintained in the 1V range during operation in order to ensure the measurement error performance. The common mode signals should be adapted to respect both the previous conditions and the differential input voltage range. For best performance, the common mode signals should be referenced to AGND. The current channel comprises a PGA on the front-end to allow for smaller signals to be measured without additional signal conditioning. The maximum differential voltage specified on Channel 0 is equal to 470 mV/Gain (see Table 4-1). The maximum peak voltage specified on Channel 1 is equal to 660 mV. Both ADCs have a 16-bit resolution, allowing wide input dynamic range sensing. The oversampling ratio of both converters is 64. Both converters are continuously converting during normal operation. When the MCLR pin is low, both converters will be in Reset and output code 0x0000h. If the voltage at the inputs of the ADC is larger than the specified range, the linearity is no longer specified. However, the converters will continue to produce output codes until their saturation point is reached. The DC saturation point is around 700 mV for Channel 0 and 1V for Channel 1, using internal voltage reference. The clocking signals for the ADCs are equally distributed between the two channels in order to minimize phase delays to less than 1 MCLK period (see Section 3.2 "High-Pass Filter Input Logic Pin (HPF)"). The SINC filters main notch is positioned at MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing the user to be able to measure wide harmonic content on either channel. The magnitude response of the SINC filter is shown in Figure 4-2.
0 -20 -40 -60 -80 -100 -120 0 5 10 15 20 25 30 Frequency (kHz)
TABLE 4-1:
G1 0 0 1 1 G0 0 1 0 1
MCP3905 GAIN SELECTIONS
CH0 Gain 1 2 8 16 Maximum CH0 Voltage 470 mV 235 mV 60 mV 30 mV
TABLE 4-2:
G1 0 0 1 1 G0 0 1 0 1
MCP3906 GAIN SELECTIONS
CH0 Gain 1 32 8 16 Maximum CH0 Voltage 470 mV 15 mV 60 mV 30 mV
FIGURE 4-2: SINC Filter Magnitude Response (MCLK = 3.58 MHz).
4.3
Normal Mode Rejection (dB)
Ultra-Low Drift VREF
4.2
16-Bit Delta-Sigma ADCs
The ADCs used in the MCP3905/06 for both current and voltage channel measurements are delta-sigma ADCs. They comprise a second-order, delta-sigma modulator using a multi-bit DAC and a third-order SINC filter. The delta-sigma architecture is very appropriate for the applications targeted by the MCP3905, because it is a waveform-oriented converter architecture that can offer both high linearity and low distortion performance throughout a wide input dynamic range. It also creates minimal requirements for the anti-aliasing filter design. The multi-bit architecture used in the ADC minimizes quantization noise at the output of the converters without disturbing the linearity.
The MCP3905/06 contains an internal voltage reference source specially designed to minimize drift over temperature. This internal VREF supplies reference voltage to both current and voltage channel ADCs. The typical value of this voltage reference is 2.4V, 100 mV. The internal reference has a very low typical temperature coefficient of 15 ppm/C, allowing the output frequencies to have minimal variation with respect to temperature since they are proportional to (1/VREF). REFIN/OUT is the output pin for the voltage reference. Appropriate bypass capacitors must be connected to the REFIN/OUT pin for proper operation (see Section 5.0 "Applications Information"). The voltage reference source impedance is typically 4 k, which enables this voltage reference to be overdriven by an external voltage reference source.
DS21948C-page 12
(c) 2005 Microchip Technology Inc.
MCP3905/06
If an external voltage reference source is connected to the REFIN/OUT pin, the external voltage will be used as the reference for both current and voltage channel ADCs. The voltage across the source resistor will then be the difference between the internal and external voltage. The allowed input range for the external voltage source goes from 2.2V to 2.6V for accurate measurement error. A VREF value outside of this range will cause additional heating and power consumption due to the source resistor, which might affect measurement error.
4.5
High-Pass Filters and Multiplier
4.4
Power-On Reset (POR)
Normal Mode Rejection (dB)
The MCP3905/06 contains an internal POR circuit that monitors analog supply voltage AVDD during operation. This circuit ensures correct device startup at system power-up/power-down events. The POR circuit has built-in hysteresis and a timer to give a high degree of immunity to potential ripple and noise on the power supplies, allowing proper settling of the power supply during power-up. A 0.1 F decoupling capacitor should be mounted as close as possible to the AVDD pin, providing additional transient immunity (see Section 5.0 "Applications Information"). The threshold voltage is typically set at 4V, with a tolerance of about 5%. If the supply voltage falls below this threshold, the MCP3905/06 will be held in a Reset condition (equivalent to applying logic `0' on the MCLR pin). The typical hysteresis value is approximately 200 mV in order to prevent glitches on the power supply. Once a power-up event has occurred, an internal timer prevents the part from outputting any pulse for approximately 1s (with MCLK = 3.58 MHz), thereby preventing potential metastability due to intermittent resets caused by an unsettled regulated power supply. Figure 4-3 illustrates the different conditions for a power-up and a power-down event in the typical conditions.
AVDD
The active (real) power value is extracted from the DC instantaneous power. Therefore, any DC offset component present on Channel 0 and Channel 1 affects the DC component of the instantaneous power and will cause the real-power calculation to be erroneous. In order to remove DC offset components from the instantaneous power signal, a high-pass filter has been introduced on each channel. Since the highpass filtering introduces phase delay, identical highpass filters are implemented on both channels. The filters are clocked by the same digital signal, ensuring a phase difference between the two channels of less than one MCLK period. Under typical conditions (MCLK = 3.58 MHz), this phase difference is less than 0.005, with a line frequency of 50 Hz. The cut-off frequency of the filter (4.45 Hz) has been chosen to induce minimal gain error at typical line frequencies, allowing sufficient settling time for the desired applications. The two high-pass filters can be disabled by applying a logic `0' to the HPF pin.
0 -5 -10 -15 -20 -25 -30 -35 -40 0.1 1 10 Frequency (Hz) 100 1000
FIGURE 4-4: HPF Magnitude Response (MCLK = 3.58 MHz).
The multiplier output gives the product of the two highpass-filtered channels, corresponding to instantaneous active (real) power. Multiplying two sine wave signals by the same frequency gives a DC component and a 2 component. The instantaneous power signal contains the active (real) power of its DC component, while also containing 2 components coming from the line frequency multiplication. These 2 components come for the line frequency (and its harmonics) and must be removed in order to extract the real-power information. This is accomplished using the low-pass filter and DTF converter.
5V 4.2V 4V
1s
0V DEVICE MODE
RESET
NO PULSE OUT
Time PROPER OPERATION RESET
FIGURE 4-3:
Power-on Reset Operation.
(c) 2005 Microchip Technology Inc.
DS21948C-page 13
MCP3905/06
4.6 Low-Pass Filter and DTF Converter
The output of the low-pass filter is accumulated in the DTF converter. This accumulation is compared to a different digital threshold for FOUT0/1 and HFOUT, representing a quantity of real energy measured by the part. Every time the digital threshold on FOUT0/1 or HFOUT is crossed, the part will output a pulse (See Section 4.7 "FOUT0/1 and HFOUT Output Frequencies"). The equivalent quantity of real energy required to output a pulse is much larger for the FOUT0/1 outputs than the HFOUT. This is such that the integration period for the FOUT0/1 outputs is much larger. This larger integration period acts as another low-pass filter so that the output ripple due to the 2 components is minimal. However, these components are not totally removed, since realized low-pass filters are never ideal. This will create a small jitter in the output frequency. Averaging the output pulses with a counter or a Microcontroller Unit (MCU) in the application will then remove the small sinusoidal content of the output frequency and filter out the remaining 2 ripple. HFOUT is intended to be used for calibration purposes due to its instantaneous power content. The shorter integration period of HFOUT demands that the 2 component be given more attention. Since a sinusoidal signal average is zero, averaging the HFOUT signal in steady-state conditions will give the proper real energy value.
The MCP3905/06 low-pass filter is a first-order IIR filter that extracts the active (real) power information (DC component) from the instantaneous power signal. The magnitude response of this filter is detailed in Figure 45. Due to the fact that the instantaneous power signal has harmonic content (coming from the 2 components of the inputs), and since the filter is not ideal, there will be some ripple at the output of the low-pass filter at the harmonics of the line frequency. The cut-off frequency of the filter (8.9 Hz) has been chosen to have sufficient rejection for commonly-used line frequencies (50 Hz and 60 Hz). With a standard input clock (MCLK = 3.58 MHz) and a 50 Hz line frequency, the rejection of the 2 component (100 Hz) will be more than 20 dB. This equates to a 2 component containing 10 times less power than the main DC component (i.e., the average active (real) power).
0 -5 -10 -15 -20 -25 -30 -35 -40 0.1 1 10 Frequency (Hz) 100 1000
FIGURE 4-5: LPF Magnitude Response (MCLK = 3.58 MHz).
Normal Mode Rejection (dB)
DS21948C-page 14
(c) 2005 Microchip Technology Inc.
MCP3905/06
4.7 FOUT0/1 and HFOUT Output Frequencies
For a given DC input V, the DC and RMS values are equivalent. For a given AC input signal with peak-topeak amplitude of V, the equivalent RMS value is V/sqrt(2), assuming purely sinusoidal signals. Note that since the active (real) power is the product of two RMS inputs, the output frequencies of an AC signal is half that of the DC equivalent signal, again assuming purely sinusoidal AC signals. The constant FC depends on the FOUT0 and FOUT1 digital settings. Table 4-3 shows FOUT0/1 output frequencies for the different logic settings.
The thresholds for the accumulated energy are different for FOUT0/1 and HFOUT (i.e., they have different transfer functions). The FOUT0/1 allowed output frequencies are quite low in order to allow superior integration time (see Section 4.6 "Low-Pass Filter and DTF Converter"). The FOUT0/1 output frequency can be calculated with the following equation:
EQUATION 4-1:
FOUT FREQUENCY OUTPUT EQUATION
8.06 x V0 x V 1 x G x F C F OUT ( Hz ) = ---------------------------------------------------------2 ( VREF ) Where: V0 = the RMS differential voltage on Channel 0 V1 = the RMS differential voltage on Channel 1 G = the PGA gain on Channel 0
(current channel)
FC = the frequency constant selected VREF = the voltage reference
TABLE 4-3:
F1 0 0 1 1 F0 0 1 0 1
OUTPUT FREQUENCY CONSTANT FC FOR FOUT0/1 (VREF = 2.4V)
FC (Hz) MCLK/221 MCLK/220 MCLK/2 MCLK/2
19 18
FC (Hz) (MCLK = 3.58 MHz) 1.71 3.41 6.83 13.66
FOUT Frequency (Hz) with Full-Scale DC Inputs 0.74 1.48 2.96 5.93
FOUT Frequency (Hz) with Full-Scale AC Inputs 0.37 0.74 1.48 2.96
(c) 2005 Microchip Technology Inc.
DS21948C-page 15
MCP3905/06
The high-frequency output HFOUT has lower integration times and, thus, higher frequencies. The output frequency value can be calculated with the following equation:
MINIMAL OUTPUT FREQUENCY FOR NO-LOAD THRESHOLD
The MCP3905/06 also includes, on each output frequency, a no-load threshold circuit that will eliminate any creep effects in the meter. The outputs will not show any pulse if the output frequency falls below the no-load threshold. The minimum output frequency on FOUT0/1 and HFOUT is equal to 0.0015% of the maximum output frequency (respectively FC and HFC) for each of the F2, F1 and F0 selections (see Table 4-3 and Table 4-4); except when F2, F1, F0 = 011. In this last configuration, the no-load threshold feature is disabled. The selection of FC will determine the start-up current load. In order to respect the IEC standards requirements, the meter will have to be designed to allow start-up currents compatible with the standards by choosing the FC value matching these requirements. For additional applications information on no-load threshold, startup current and other meter design points, refer to AN994, "IEC Compliant Active Energy Meter Design Using The MCP3905/6", (DS00994).
EQUATION 4-2:
HFOUT FREQUENCY OUTPUT EQUATION
8.06 x V0 x V 1 x G x HFC HF OUT ( Hz ) = --------------------------------------------------------------2 ( VREF ) Where: V0 = the RMS differential voltage on Channel 0 V1 = the RMS differential voltage on Channel 1 G = the PGA gain on Channel 0
(current channel)
FC = the frequency constant selected VREF = the voltage reference The constant HFC depends on the FOUT0 and FOUT1 digital settings with the Table 4-4. The detailed timings of the output pulses are described in the Timing Characteristics table (see Section 1.0 "Electrical Characteristics" and Figure 1-1).
TABLE 4-4:
F2 0 0 0 0 1 1 1 1 F1 0 0 1 1 0 0 1 1
OUTPUT FREQUENCY CONSTANT HFC FOR HFOUT (VREF = 2.4V)
F0 0 1 0 1 0 1 0 1 HFC 64 x FC 32 x FC 16 x FC 2048 x FC 128 x FC 64 x FC 32 x FC 16 x FC HFC (Hz) MCLK/215 MCLK/215 MCLK/215 MCLK/27 MCLK/216 MCLK/216 MCLK/2 MCLK/2
16 16
HFC (Hz) (MCLK = 3.58 MHz) 109.25 109.25 109.25 27968.75 219.51 219.51 219.51 219.51
HFOUT Frequency (Hz) with full-scale AC Inputs 27.21 27.21 27.21 6070.12 47.42 47.42 47.42 47.42
DS21948C-page 16
(c) 2005 Microchip Technology Inc.
MCP3905/06
5.0
5.1
APPLICATIONS INFORMATION
Meter Design using the MCP3905/06
For all applications information, refer to AN994, "IEC Compliant Active Energy Meter Design Using The MCP3905/6" (DS00994). This application note includes all required energy meter design information, including the following: Meter rating and current sense choices Shunt design PGA selection F2, F1, F0 selection Meter calibration Anti-aliasing filter design Compensation for parasitic shunt inductance EMC design Power supply design No-load threshold Start-up current Accuracy testing results from MCP3905-based meter * EMC testing results from MCP3905-based meter * * * * * * * * * * * *
(c) 2005 Microchip Technology Inc.
DS21948C-page 17
MCP3905/06
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
24-Lead SSOP Examples:
XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
MCP3905 e3 I/SS^^ 0539256
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS21948C-page 18
(c) 2005 Microchip Technology Inc.
MCP3905/06
24-Lead Plastic Shrink Small Outline (SS) (SSOP)
E p E1
D B n 2 1
A c
A2 A1 L
Number of Pins Pitch
Units Dimension Limits n p
MIN
INCHES NOM 24 .026 BSC.
MAX
MIN
MILLIMETERS* NOM 24 0.65 BSC.
MAX
1.86 1.73 .078 A .073 Overall Height .068 1.99 1.73 1.68 .070 .066 .068 A2 1.78 Molded Package Thickness 0.05 0.13 .005 .008 .002 Standoff A1 0.21 7.80 7.65 .311 .307 .301 E 7.90 Overall Width 5.30 5.20 .212 .209 E1 .205 5.38 Molded Package Width 8.20 8.07 .328 .323 Overall Length .318 D 8.33 L .025 .030 .037 0.63 0.75 0.95 Foot Length c .004 .006 - 0.09 0.15 - Lead Thickness 0 4 8 0 4 8 Foot Angle B .010 - .015 0.25 - 0.38 Lead Width * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M JEDEC Equivalent: MO-150 Revised 9-14-05 Drawing No. C04-132
(c) 2005 Microchip Technology Inc.
DS21948C-page 19
MCP3905/06
NOTES:
DS21948C-page 20
(c) 2005 Microchip Technology Inc.
MCP3905/06
APPENDIX A: REVISION HISTORY
Revision C (October 2005)
* Added references to MCP3905/06 throughout document.
Revision B (August 2005)
* Replace Figures 2-1 thru 2-6 in Section 2.0 "Typical Performance Curves"
Revision A (July 2005)
* Original Release of this Document.
(c) 2005 Microchip Technology Inc.
DS21948C-page 21
MCP3905/06
NOTES:
DS21948C-page 22
(c) 2005 Microchip Technology Inc.
MCP3905/06
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range /XX Package Examples:
a) b)
Energy-Metering IC Energy-Metering IC (Tape and Reel) Energy-Metering IC Energy-Metering IC (Tape and Reel)
MCP3905-I/SS:
Device:
MCP3905: MCP3905T: MCP3906: MCP3906T:
Industrial Temperature, 24LD SSOP. MCP3905T-I/SS: Tape and Reel, Industrial Temperature, 24LD SSOP. Industrial Temperature, 24LD SSOP. MCP3906T-I/SS: Tape and Reel, Industrial Temperature, 24LD SSOP.
a) b)
MCP3906-I/SS:
Temperature Range:
I
= -40C to +85C
Package:
SS = Plastic Shrink Small Outline (209 mil Body), 24-lead
(c) 2005 Microchip Technology Inc.
DS21948C-page 23
MCP3905/06
NOTES:
DS21948C-page 24
(c) 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2005 Microchip Technology Inc.
DS21948C-page 25
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 604-646-8870 Fax: 604-646-5086 Philippines - Manila Tel: 632-634-9065 Fax: 632-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-352-30-52 Fax: 34-91-352-11-47 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
**DS21948C**
08/24/05
DS21948C-page 26
(c) 2005 Microchip Technology Inc.

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